The present invention relates generally to integrated circuit (IC) designs, and more particularly to a phase-locked loop (PLL) circuit with a mixed mode filter for reducing the implementation area of the PLL circuit.
PLL circuits are commonly used in circuits that generate a high-frequency signal with a frequency being an accurate multiple of the frequency of a reference signal. PLL circuits can also be found in applications where the phase of the output signal has to track the phase of the reference signal, hence the name phase-locked loop. For example, the PLL circuit can be used in a radio receiver or transmitter for generating a local oscillator signal, which is a multiple of a stable, low-noise and often temperature-compensated reference signal. As another example, the PLL circuit can also be used for clock recovery applications in digital communication systems, disk-drive read-channels, etc.
A conventional PLL circuit typically includes a phase and frequency detector, a charge pump, a loop filter, a voltage control oscillator and a feedback divider. The loop filter can be either analog or digital. The analog loop filter can be a passive filter composed of inductors, capacitors, and resistors, or an active filter composed of resistors, capacitors, and amplifiers. The digital loop filter is composed of building blocks, such as adders, delay units, and multipliers.
The analog loop filter combines a resistor in series with a capacitor. The stability of the analog PLL circuit is proportional to the values of the resistor and capacitor. Conventionally, the value of capacitor is set approximately from 100 pF to 300 pF in order to avoid instability. The large capacitor causes the PLL circuit to be large in size.
The digital loop filter combines a digital amplifier, adder and delay unit, and is realizable in a smaller area compared to the analog loop filter. However, a digital-to-analog converter requires an interface with the analog voltage control oscillator. The area of digital-to-analog converter is small at low resolutions and large at high resolutions. In order to obtain a high accuracy, the digital-to-analog converter for the PLL circuit needs to have a high resolution (10˜14 bits). Thus, the area occupied by the digital PLL circuit is large due to the high resolution digital-to-analog converter, in spite of the small area occupied by the digital loop filter.
As such, it is desirable to have a PLL circuit that provides high accuracy and occupies minimum areas.